haven't they always sorta supported this through coprocessor instructions?
What I find most funny about ARM moving to allow custom ISA extensions is that in last year's "risc-v basics" smear campaign one of their main arguments against RISC-V was that it'd be unfathomably bad that RISC-V allows custom ISA extensions bc that would lead to fragmentation.
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That campaign backfired and didn’t last very long.
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FWIW, I think the argument was correct. I wish RISC-V and others would explore ways to do custom extensions that don't clash with ISA encoding space.
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For instance having them all take a "coprocessor address" operand in a fixed register (after all, there's a huge abundance of registers) that could even be resolved at runtime for the particular cpu model.
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everything is bad until you can do it. certain people who will remain nameless argued that high code density was bad until the compressed instructions spec came out and macro fusion was added to a specific rocket core generator derivative.
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