I'm going to @hackaday supercon! Working on an FPGA based badge based on @esden's #icebreaker and @fpga_dave 's LCD pmod. Today I got some insight into timing from @oe1cxw and now I have a smooooth scrolling frame buffer.https://youtu.be/P0grX_liTUM
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He probably zero pads to 512 samples.
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Those white bars, could that be zero padding? FLASH goes to logic "1" for default, erased state, right? You spend energy writing the bits to 0? So, default, blank flash page would be all FF's, which any RGB display might show as white bands- no idea.
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Sliding DFTs are very easy to do in FPGA, perfect for signals like audio where the ratio of clock speed to sample rate can be very large. Good choice.
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