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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. matthew venn‏ @matthewvenn 24 Sep 2019
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      I'm going to @hackaday supercon! Working on an FPGA based badge based on @esden's #icebreaker and @fpga_dave 's LCD pmod. Today I got some insight into timing from @oe1cxw and now I have a smooooth scrolling frame buffer.https://youtu.be/P0grX_liTUM 

      3 replies 9 retweets 40 likes
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    2. matthew venn‏ @matthewvenn 30 Sep 2019
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      #FPGA twitter quiz! My badge is going to be an FFT audio analyser with waterfall output. I've just fixed a bug that ruined exactly the last 3/4 of the FFT output. Any guesses as to what it was? Here's a photo showing a square sweep over 4 seconds.pic.twitter.com/UCh6OIOCSM

      3 replies 3 retweets 14 likes
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    3. Zip CPU‏ @zipcpu 30 Sep 2019
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      Replying to @matthewvenn @hackaday and

      Which way is the raster supposed to move: left to right, right to left (like my example did), top to bottom, or bottom up?

      1 reply 0 retweets 0 likes
    4. Zip CPU‏ @zipcpu 30 Sep 2019
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      Replying to @zipcpu @matthewvenn and

      Also, is it supposed to scroll across the screen, or forever overwrite what's there? Is it supposed to show one new line of data at a time, or more--something like a block of data at a time?

      1 reply 0 retweets 0 likes
    5. matthew venn‏ @matthewvenn 30 Sep 2019
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      Replying to @zipcpu @hackaday and

      I have the FFT setup with 320 bins, one for each pixel along the bottom of the screen. Every screen update the display is scrolled up one pixel and new results written to the bottom line.

      1 reply 0 retweets 2 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 30 Sep 2019
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      Replying to @matthewvenn @zipcpu and

      Now I am curious. Assuming it's a Radix-2 FFT, how can you have a number of bins that isn't a power of two?

      7:05 AM - 30 Sep 2019
      • 1 Like
      • Piotr Esden-Tempski @esden@chaos.social
      2 replies 0 retweets 1 like
        1. New conversation
        2. 天 Oğuz Meteer 天‏ @BitlogIT 30 Sep 2019
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          Replying to @oe1cxw @matthewvenn and

          He probably zero pads to 512 samples.

          1 reply 0 retweets 1 like
        3. Tom Fleet‏ @tomfleet 30 Sep 2019
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          Replying to @BitlogIT @oe1cxw and

          Those white bars, could that be zero padding? FLASH goes to logic "1" for default, erased state, right? You spend energy writing the bits to 0? So, default, blank flash page would be all FF's, which any RGB display might show as white bands- no idea.

          0 replies 0 retweets 2 likes
        4. End of conversation
        1. New conversation
        2. matthew venn‏ @matthewvenn 30 Sep 2019
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          Replying to @oe1cxw @zipcpu and

          it's a sliding DFT https://www.comm.utoronto.ca/~dimitris/ece431/slidingdft.pdf …

          2 replies 0 retweets 4 likes
        3. Eric Brombaugh‏ @ebrombaugh 30 Sep 2019
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          Replying to @matthewvenn @oe1cxw and

          Sliding DFTs are very easy to do in FPGA, perfect for signals like audio where the ratio of clock speed to sample rate can be very large. Good choice.

          0 replies 0 retweets 2 likes
        4. End of conversation

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