Again, with your suggestions added and the previous winner removed, because twitter allows max 4 options. reg [3:0] foo; foo != 15 && foo != 0
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I think I’d leave as is because the synthesiser will do something smart (right?) and it’s then about clarity for humans.
It's just for fun. Logic synthesis will produce the same circuit in all cases. Especially for such a small vector.
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I write embedded C with a mental model of what the compiler will do and strive for readability where the compiler needs no hints. I’m now trying to build a mental model of a Verilog synthesiser.
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It’s hard to decide on readability, because what’s a clever way of expressing something today can trip yourself up in the future.
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