I think I’d leave as is because the synthesiser will do something smart (right?) and it’s then about clarity for humans.
Again, with your suggestions added and the previous winner removed, because twitter allows max 4 options. reg [3:0] foo; foo != 15 && foo != 0
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It's just for fun. Logic synthesis will produce the same circuit in all cases. Especially for such a small vector.
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Does ~&foo reduce correctly or do you need ~(&foo)? I’d go with ~(&foo) && |foo to mean “not all and not none”
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Unary operators bind tight
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My foo-fu is weak at the moment. Just too tired to think about it right now.
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I would never actually use option 3. I just stumbled upon it by mistake when trying to come up with the most convoluted solution of xor statements. I do like how simple and very non-intuitive it is
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Personally I'd never use any of those options. They're not readable to me. Only foo != 15 && foo != 0, or even foo != 4'd15 && foo != 4'd0. I never trust the compiler to know what I want.
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I might even put parens around each term because I know the state of Verilog processors is stuck in the last millenium
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For this example #1 is more intuitive. Although #3 gives more control to optimize the gates irrespective of compiler.
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