Gonna have to stop calling it "RISC" 
I wrote Verilog reference implementations of all proposed RISC-V bitmanip instructions. I'm pretty happy with the results. The cores are permissively licensed under ISC license. See chapter 3 of https://raw.githubusercontent.com/riscv/riscv-bitmanip/master/bitmanip-draft.pdf … or https://github.com/riscv/riscv-bitmanip/tree/master/verilog … for more information.pic.twitter.com/qOviqlYlmc
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I once or twice jokingly called it the "RISC-V CISC Extension". Not everyone was amused.
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Nice! Looks good. Maybe even Andrew will be convinced:-) Have you looked at the size of cut-down rev, rev8, gorc.b for simple?
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I have not tested this, so there may be bugs, but this synthesizes to 165 gates using that same cell library.pic.twitter.com/LajM1l78Tx
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