FV is still a bit of black magic. Comitted a three-liner that makes memory accesses 1 cycle (~1%) faster on SERV. Suddenly the verification time goes from a comfortable 1h to...I don't know since I run out of battery after four hours when it had completed 16% of the tests
Finding a model often takes longer than finding an unsat kernel. In other words: it may be that you have broken your design in a nontrivial way.
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Interesting. I'll see what comes up when I rerun the whole thing. My theory was that the extra cycle would give room for another instruction in the specified number of steps so that the space to analyze would be much larger
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Looking forward to your results. Is a post of a small example possible, without herculean effort ?
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