Alright. According to my analysis SERV uses 1456 gates (+ one 4x288 bits of RAM. Unfortunately I have no idea whatsoever if this is the correct way to do a gate count.
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Hmm.. I've been typing random yosys command all morning but hadn't seen that. Doesn't work for me though. Maybe need a newer yosys version
"stat -tech cmos" is pretty new, and I merged changes related to it just a few hours ago. So it's not unlikely that you'll need to update Yosys. Note that some of the gate costs (mux, xor) are conservative. More efficient implementations using pass transistors exist.
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Cool, so newbie question here. Am I supposed to run synth first? And then abc -g something? Can it do a gate count on my RF SRAM or should I handle that separately?
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Yes, run "synth" first, then "abc -g cmos". See here for a usage example: https://github.com/riscv/riscv-bitmanip/blob/master/verilog/rvb_clmul/synth.py … As I'm not familiar with the details of your flow I'm assuming that RAM is just a black box for Yosys in your case. In this case you'd have to handle it separately.
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