Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

What is a word for a pace even slower than glacial? @jangray isn't the only one doing kilocore RISC-V in FPGA. I've hacked a version of my Glacial RISC-V core to run 1024 cores in an XC7A50. They're run serially, though, not in parallel.

Awesome. Can you please tell us more?

As you know, my Glacial core is heavily vertically microcoded. It was written only to compete in the low-resource category of the previous RISC-V core competition. 1/

Glacial takes four clock cycles to execute one microinstruction, so hundreds of clock cycles to execute each RISC-V instruction. 2/

I got jealous of your kilocore work but can't afford any FPGAs bigger than XC7A100. So I thought, I can make Glacial into a sequential multithread core. With 1024 "hardware" threads, now each thread takes a few hundred thousand clock cycles to execute one RISC-V instruction. 3/

It should fit in even a tiny FPGA with external RAM. You can scale the number of threads from 1 to however much memory you can afford, and of course it slows down commensurately. 4/

The original single-thread Glacial might actually be useful in very limited circumstances. I can't imagine any good use for a 1024-thread Glacial, but maybe a small number of threads could be useful. 5/

Could be an excellent cheap test platform for parallel algorithms. I imagine right now you schedule threads round-robin. Would it be possible to instead just schedule threads randomly?