What is a word for a pace even slower than glacial? @jangray isn't the only one doing kilocore RISC-V in FPGA. I've hacked a version of my Glacial RISC-V core to run 1024 cores in an XC7A50. They're run serially, though, not in parallel.
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The original single-thread Glacial might actually be useful in very limited circumstances. I can't imagine any good use for a 1024-thread Glacial, but maybe a small number of threads could be useful. 5/
Could be an excellent cheap test platform for parallel algorithms. I imagine right now you schedule threads round-robin. Would it be possible to instead just schedule threads randomly?
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Sure. In Glacial, to minimize resource utilization, the microcode, "workspace" (GPRs, CSRs, and scratch), and "real memory" are all in one address space. 1/
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In Tectonic, I just have a counter that increments once every four clocks (single microinstruction). The counter provides part of the hardware memory address when accessing the workspace or "real memory", but not the microcode. 2/
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I think a more practical solution would be to take a more conventional RISC-V core design, perhaps with a 3 stage pipeline, and turn it into a barrel processor, or, with fancier thread scheduling, something like the Ubicom IP3023.
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I'm actually currently working on a barrel processor design, but of a CISC rather than a RISC. I've considered designing a barrel RISC-V, but haven't written any HDL for one.
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