Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

Using & instead of ?: should prevent this

That would be *really* important to know! Can you please test that? (Anything that makes behavioural vs. structural implementations differ is very significant.)

Replacing the ?: with out <= in & ~{WORD_WIDTH{annul}}; means that Yosys no longer infers a sync reset, but Vivado still does infer the reset (don't have Quartus installed)

Wow. I did not expect that. Thank you for testing. I wonder what @oe1cxw would think of that difference?

This is definitely deliberate in how the pass that extracts iCE40 (and the equivalent pass I wrote for ECP5) sync SRs. It maps muxes selecting between a signal and 0/1 to reset or set; but not ANDNOT or OR gates.

It always bothered me that verilog style differences on otherwise equivalent logic guide the mapping. If the Verilog is generated from a higher level description, “style” assumptions don’t hold. I’d bypass Verilog if I could find a portable way to do it.

Yes, exactly that. And it's one of my main reasons for being sceptic towards new HDL as long as they still pass through verilog. I think a standard library with tech-specific backends is a better short-time solution