Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

Wow. I did not expect that. Thank you for testing. I wonder what @oe1cxw would think of that difference?

This is definitely deliberate in how the pass that extracts iCE40 (and the equivalent pass I wrote for ECP5) sync SRs. It maps muxes selecting between a signal and 0/1 to reset or set; but not ANDNOT or OR gates.

It always bothered me that verilog style differences on otherwise equivalent logic guide the mapping. If the Verilog is generated from a higher level description, “style” assumptions don’t hold. I’d bypass Verilog if I could find a portable way to do it.

Yes, exactly that. And it's one of my main reasons for being sceptic towards new HDL as long as they still pass through verilog. I think a standard library with tech-specific backends is a better short-time solution

Good thing nMigen doesn't pass through Verilog :)

What does nMigen output instead?

RTLIL.

Can't seem to find a description of RTLIL. Could you point me to an example, please?