This one gets never old. PSA: If you have a RISC-V processor, make sure it clears the LSB of all jump targets, not throws an illegal instruction address exception on nonzero LSB. Feels to me like more cores get this wrong than right at first.https://github.com/SymbioticEDA/riscv-formal/issues/22 …
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Isn’t there a test suite that should catch bugs like this?
Yes. Multiple. Not all of them check for this.. I guess ultimately the official risc-v compliance tests will cover this. But so far they are still under construction.