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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Eric LaForest‏ @elaforest 8 Jun 2019
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      Replying to @OlofKindgren @fpga_dave

      As always: modularization! :) And see the comments in the GitHub file below. https://github.com/laforest/Octavo/blob/master/Parts/Misc/Annuller.v … http://fpgacpu.ca/fpga/annuller.html …

      2 replies 0 retweets 3 likes
    2. Dave  🏳️‍🌈‏ @fpga_dave 8 Jun 2019
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      Replying to @elaforest @OlofKindgren

      FYI, Yosys synth_ice40 with default settings will infer a sync reset fromhttps://pastebin.com/HQFnvRcs 

      2 replies 0 retweets 2 likes
    3. Dave  🏳️‍🌈‏ @fpga_dave 8 Jun 2019
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      Replying to @fpga_dave @elaforest @OlofKindgren

      Using & instead of ?: should prevent this

      1 reply 0 retweets 0 likes
    4. Eric LaForest‏ @elaforest 8 Jun 2019
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      Replying to @fpga_dave @OlofKindgren

      That would be *really* important to know! Can you please test that? (Anything that makes behavioural vs. structural implementations differ is very significant.)

      1 reply 1 retweet 0 likes
    5. Dave  🏳️‍🌈‏ @fpga_dave 8 Jun 2019
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      Replying to @elaforest @OlofKindgren

      Replacing the ?: with out <= in & ~{WORD_WIDTH{annul}}; means that Yosys no longer infers a sync reset, but Vivado still does infer the reset (don't have Quartus installed)

      2 replies 1 retweet 3 likes
    6. Eric LaForest‏ @elaforest 8 Jun 2019
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      Replying to @fpga_dave @OlofKindgren

      Wow. I did not expect that. Thank you for testing. I wonder what @oe1cxw would think of that difference?

      1 reply 0 retweets 0 likes
    7. Dave  🏳️‍🌈‏ @fpga_dave 8 Jun 2019
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      Replying to @elaforest @OlofKindgren @oe1cxw

      This is definitely deliberate in how the pass that extracts iCE40 (and the equivalent pass I wrote for ECP5) sync SRs. It maps muxes selecting between a signal and 0/1 to reset or set; but not ANDNOT or OR gates.

      3 replies 0 retweets 3 likes
    8. Dr. Thorn‏ @iamtommythorn 8 Jun 2019
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      Replying to @fpga_dave @elaforest and

      It always bothered me that verilog style differences on otherwise equivalent logic guide the mapping. If the Verilog is generated from a higher level description, “style” assumptions don’t hold. I’d bypass Verilog if I could find a portable way to do it.

      3 replies 1 retweet 2 likes
    9. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Jun 2019
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      Replying to @iamtommythorn @fpga_dave and

      I get that, but you will have phenomena like that with every compiler. It's the same with C compilers. Even more formal methods like reactive synthesis and program synthesis will usually not produce a canonical output for a set of logical equivalent inputs.

      1 reply 0 retweets 0 likes
    10. Dr. Thorn‏ @iamtommythorn 8 Jun 2019
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      Replying to @oe1cxw @fpga_dave and

      Can you provide an example of where a mere stylistic difference makes a significant difference in what the C compiler generates?

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Jun 2019
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      Replying to @iamtommythorn @fpga_dave and

      I'm not sure I'd call replacing the ?: code with & ~{W{..}} a pure stylistic difference. But okay, if that counts: https://godbolt.org/z/5IK-SY  (This is with gcc. Clang has an opt for this. But that's my point: It's all based on pattern matching, not logic equivalence classes.)

      11:15 PM - 8 Jun 2019
      2 replies 0 retweets 0 likes
        1. New conversation
        2. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Jun 2019
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          Replying to @oe1cxw @iamtommythorn and

          Of course with all such examples one can always argue what is "significant" and what is "pure stylistic". Here is another one where the compiler has one pattern built-in but not others: https://godbolt.org/z/isRVRD 

          1 reply 0 retweets 0 likes
        3. Dr. Thorn‏ @iamtommythorn 9 Jun 2019
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          Replying to @oe1cxw @fpga_dave and

          Thanks the example! In corner A we have the single most basic feature in the device, the flip-flop, in corner B we something that is pretty exotic (hardly a guaranteed feature in a processor and far from the basic semantics of C). Not quite comparable IMhO

          0 replies 0 retweets 2 likes
        4. End of conversation
        1. Dr. Thorn‏ @iamtommythorn 9 Jun 2019
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          Replying to @oe1cxw @fpga_dave and

          That a totally legit example, nice find. I have to say that the equivalence doesn't exactly jump out at you, but yes, the compiler should have treated them the same.

          0 replies 0 retweets 1 like
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