That's very possible. I find that, rather than using set/clear lines, usually shared resources, I'm better off implementing these in logic (e.g. an Annuller) for portability and packing (and thus speed).
-
It always bothered me that verilog style differences on otherwise equivalent logic guide the mapping. If the Verilog is generated from a higher level description, “style” assumptions don’t hold. I’d bypass Verilog if I could find a portable way to do it.
I get that, but you will have phenomena like that with every compiler. It's the same with C compilers. Even more formal methods like reactive synthesis and program synthesis will usually not produce a canonical output for a set of logical equivalent inputs.
-
-
Can you provide an example of where a mere stylistic difference makes a significant difference in what the C compiler generates?
-
I'm not sure I'd call replacing the ?: code with & ~{W{..}} a pure stylistic difference. But okay, if that counts: https://godbolt.org/z/5IK-SY (This is with gcc. Clang has an opt for this. But that's my point: It's all based on pattern matching, not logic equivalence classes.)
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.