Here have some cursed Verilog codepic.twitter.com/6ux0qr2kec
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I didn't think so, but I was only 90% sure so I asked anyway :P. That code snippet looks really "fun"...
These are the "fun" ones because they are legal and should be supported by synthesis.https://twitter.com/oe1cxw/status/1123339372244422661 …
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In test2, I assume assigning to "y" instead of using always @* is deliberate. But I'm not sure why you're doing it. Is there a semantic difference between a single blocking assignment inside an "always @*" and using "assign"?
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No, there's no difference. But both versions should be supported so both versions are tested here.
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