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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. whitequark‏ @whitequark 2 Apr 2019
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      I made a detailed-ish writeup on the worst bug I have ever encountered. I've been fighting it on and off for months and the only thing I was able to do is to narrow it down somewhat. Here it is:https://community.cypress.com/message/191835 

      5 replies 4 retweets 46 likes
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    2. whitequark‏ @whitequark 2 Apr 2019
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      update: I've been fighting it for months because the bug was in the part that I considered out of scope, rip thanks @enjoy_digital ! https://github.com/GlasgowEmbedded/Glasgow/issues/89#issuecomment-479015182 …

      1 reply 2 retweets 17 likes
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    3. whitequark‏ @whitequark 2 Apr 2019
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      aaaaaaaaAAAAAAAAAAAAA IT WAS A TOOLCHAIN BUGhttps://github.com/YosysHQ/yosys/commit/6acbc016f43b1464e6322b895f16d01ed51eea18 …

      6 replies 5 retweets 36 likes
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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 3 Apr 2019
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      Replying to @whitequark

      I'm so sorry for your troubles, and anyone elses troubles who also encountered this bug. I've now merged the bug fix.

      1:07 AM - 3 Apr 2019
      1 reply 0 retweets 0 likes
        1. New conversation
        1. whitequark‏ @whitequark 3 Apr 2019
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          Replying to @oe1cxw

          yeah, it's fine, I'm mostly frustrated by my own failure to bisect it down to the toolchain by replacing the FIFO output with a counter.

          1 reply 0 retweets 0 likes
        2. whitequark‏ @whitequark 3 Apr 2019
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          Replying to @whitequark @oe1cxw

          on the other hand, this was the last part of the Glasgow gateware that made me doubt whether the PCB design is good, so it's really good it's fixed now

          0 replies 0 retweets 8 likes
          3. End of conversation

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