You might wish to chat with the defense or satellite industries--both of which regularly need FPGA tool chains that support our of date FPGAs. Updating an FPGA configuration on a satellite is all the more challenging when the FPGA is already out of date on the launch pad.
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With those I spoke to said: "We work with an in-time frozen installation of the tool which was certified back then. There is no way we could introduce a new toolchain" I guess we need to wait until they have a huge problem only we can solve.
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Yeah no one would use open source in a critical capacity with $20M on the line
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Is this a good moment in time to mention that https://als.lbl.gov/ uses some of my FOSS projects? (For example, PicoRV32 is in their safety interlocks.) CERN also uses some of my FOSS code in LHC.
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I don't know what of my other stuff, if any, is used in ALS specifically. (Those machines are also being changed constantly.) But in general LBNL is also using Yosys for various tasks and have at least started to evaluate nextpnr for ECP5.
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The reason I mentioned PicoRV32 in ALS is because safety interlocks are a pretty permanent part of the system (so I can be pretty sure it's still in there) and interlocks are a critical component, so they definitely trust those open source cores with >$20M on the line.
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