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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. [ColeJ]‏ @ColeJ71909899 25 Feb 2019
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      More Verilog Dark Magic my code is something like this: wire or_gate = X(thing1 | thing2); reg shifter[4:0] = 0; always @(posedge thing3) begin ... shifter <= shifter[1:1] = Xor_gate; ... end Despite "or_gate" only being used in the above code, (cont)

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    2. [ColeJ]‏ @ColeJ71909899 25 Feb 2019
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      Putting a "!" in the "X" spot messes up other signals along with or_gate. Also, behavior is different depending on which "X" is replaced with a "!". I understand that changes in placement can mess up other signals, but how does adding an inverter change placement (cont)

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    3. [ColeJ]‏ @ColeJ71909899 25 Feb 2019
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      when inverters are merely part of existing LUTs? Any idea as to why this happens @fpga_dave @oe1cxw? I'm going to switch from arachne to nextpnr which should hopefully fix it or provide more insight.

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    4. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 25 Feb 2019
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      Replying to @ColeJ71909899 @fpga_dave

      (1) "A <= B = C;" isn't valid Verilog code (2) Any change in the netlist can, and likely will, change placement and routing. Even things like just renaming entities or inserting newlines (which changes source location annotations).

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    5. [ColeJ]‏ @ColeJ71909899 25 Feb 2019
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      Replying to @oe1cxw @fpga_dave

      Oops I messed up that line it should be shifter[1:1] <= Xor_gate; Huh, I didn't know that PNR output could depend on those variables. That a weird explanation for weird behavior

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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 25 Feb 2019
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      Replying to @ColeJ71909899 @fpga_dave

      A lot of things in place an route depend on the order things like cells are processed. Inferred cells are assigned auto-generated names that can contain things like an index. So adding an additional inverter can change those cell names, and thus change the sorting order.

      9:48 PM - 25 Feb 2019
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      • gojimmypi [ColeJ]
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