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when inverters are merely part of existing LUTs?
Any idea as to why this happens @fpga_dave @oe1cxw?
I'm going to switch from arachne to nextpnr which should hopefully fix it or provide more insight.
(1) "A <= B = C;" isn't valid Verilog code (2) Any change in the netlist can, and likely will, change placement and routing. Even things like just renaming entities or inserting newlines (which changes source location annotations).
![[ColeJ]](https://pbs.twimg.com/profile_images/1043000626056065024/vDRPnUpt_normal.jpg)
Oops I messed up that line it should be shifter[1:1] <= Xor_gate; Huh, I didn't know that PNR output could depend on those variables. That a weird explanation for weird behavior
A lot of things in place an route depend on the order things like cells are processed. Inferred cells are assigned auto-generated names that can contain things like an index. So adding an additional inverter can change those cell names, and thus change the sorting order.
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