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Don't get mad at these guys. For anything that is tooling for safety critical stuff certification and strict quality control is needed. That sometimes means, that a bug report does not get priority. Hangs are nasty but they don't directly lead to failures.
(1) I am not mad at anyone. I'm just stating facts. (2) Two of the four bugs we are discussing here are cases where Vivado silently produces incorrect synthesis results, as are most of the bugs I found with VlogHammer. One of those two I first reported in 2014.
If that's the case with the FPGAs, then that's probably also the case with digital logic based circuits, CPUs, etc. that are "hardwired" at semiconductor foundry and that are used at car ABS breaks, heart pace makers, things that have a label "safety critical" in sales talk.
My practical takeaway from this thread is that I should really try to think of algorithm development with some kind of watchdog induced reset in mind. Not just to withstand power failures, but in the context of being efficient/fast at booting @ regular intervals. Bast booting.
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