semi-related: I feel like SystemVerilog Assertions strongly resemble regular expressions in the way they're designed, which is both a blessing and a curse
That's literally the theoretical foundation for SVA properties: regexes over strings where the symbols in the alphabet represent boolean expressions over the state space. (Only that the strings can be infinite in length, which makes it a so-called omega-regular language.)
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Thanks. Twitter will use this to make your timeline better. UndoUndo
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Are assertions in SV supported by iverilog these days ?
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Unfortunately no, not even immediate assertions.
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@oe1cxw what is a good learning resource for SystemVerilog, assertions and otherwise? -
I'm not sure. I myself learned most of it from the IEEE 1800 Std document. Can't really recommend that approach tho.
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