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I did mean that Xilinx only accept SR for projects using UltraScale, so to report a generic issue one still needd to say the problem is related to active project with ultrascale device
I still don't quite understand what you want me to do. Just click "new project" in Vivado, add the Verilog file, and click synthesis. The two cases that hang will hang, for the other ones, click open synth design and view schematic to see the constant outputs. Or simply this:pic.twitter.com/Fx8c2kI6Gg
If by "SR" U mean "service request", then this thread demonstrates extra vividly, how stupid the situation is with the closed source EDA software. Come on, a competent guy like the @oe1cxw putting @XilinxInc 2 its Bug findings description Tweet SHOULD BE ENOUGH to report bugs.
The megacorporations have nice "chicks" or otherwise beauties at their reception desks, full time paid Public Relations/propaganda employees on their payroll, and yet they can't hire some tech student to pick up bug reports from social media hints. That's a matter of attitude!
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