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There are no SR possible for 7 series or earlier. To submit a SR the bug must be replicated on UltraScale, then we could submit SR for you
All of those bugs are for the HDL front-end. Nothing in any of those 4 descriptions mentions any specific series of devices. What gives you the impression that those reports are specific to 7 series?
I did mean that Xilinx only accept SR for projects using UltraScale, so to report a generic issue one still needd to say the problem is related to active project with ultrascale device
I still don't quite understand what you want me to do. Just click "new project" in Vivado, add the Verilog file, and click synthesis. The two cases that hang will hang, for the other ones, click open synth design and view schematic to see the constant outputs. Or simply this:pic.twitter.com/Fx8c2kI6Gg
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