it's kind of really annoying how today's FPGA tools appear to be optimized for building handwritten code, and tend to exhibit rather pathological, and completely unpredictable, behavior when fed machine-generated code
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This is at least not true for Vivado and HDLWorks EASE.
It is *definitely* true for Vivado. And they usually take 2+ years to fix those incorrect synthesis bugs. And they haven't fixed any of the synthesis issues that I have reported since I lost the ability to create SRs when I left my previous job.
