Hey @oe1cxw -- I'm trying to poke at constraints in nextpnr (like the ringosc example in your slides) -- is there a way to attach attributes to inferred flops, adders, etc in verilog or do I need to work with the SB_* entities to make this stuff work?
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So far, from verilog, I seem to only be able to associate attributes with wires/nets, not anything that becomes cells...
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Replying to @dnaltews
It's hard to keep track of inferred logic. Your best chance is probably to simply put the logic in question in a separate module. And only flatten it into the design at the very end of your synthesis script, after setting the attribute on every cell in the module.
12:57 AM - 1 Jan 2019
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