as far as i can tell this is more or less how you're supposed to do signed math in verilog. (i could make i_imm8 signed, and i could replace $signed(1) with a 1'bs1, but neither is much of improvement)
thanks i hate itpic.twitter.com/mKRwGeXrih
jfyi, unsized integer literals such as "1" are already signed. (Also, "unsized integer literals are at least 32 bits wide, which is likely the cause why you needed the and-mask.) Afaict the following works. (But you'll get angry at Verilog if I explain what {...} does there. :)pic.twitter.com/HH0A31RzuQ
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I am already very angry, so please explain while I fix the specification to be, uh, very marginally less ugly
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So the {...} is just the regular concatenation operator, but with only one argument, so the isn't much to concatenate in fact. But the arguments to that operator are self-signed and self-sized, so the stuff outside {..} doesn't influence the signedness or size of the argument.
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