Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

hahaha, so in nMigen simulator, it turns out that I've implemented VHDL concurrency semantics (http://insights.sigasi.com/opinion/jan/vhdls-crown-jewel.html …); I just tried to make sure it does something sensible and as usual, Verilog does not do anything sensible, ever

of course, this is now causing a major issue, namely that my translation layer that *should* make Verilog simulators do something sensible, either causes them to miss signal updates, or causes them to go into infinite loops I hate Verilog so much

do you think you can take a look at this? it's a mid-size repro but the relevant part is really small and easy to understand