this is the sort of code that FPGA vendors provide in their technotes as the code you are expected to write. yes, with the mixed blocking and non-blocking assignment... (Lattice TN1250)pic.twitter.com/HtOjjiw3Qp
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Oh dear. Am I correct in understanding that using any blocking assignment in a clocked always block, where the value is used outside the block, can always lead to a race condition, because the simulation order of triggered clocked always blocks is unknown?
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Thanks! So that's another (and I guess the main) underlying reason for the dogma about where to use (non-)blocking assignments. It became plainly obvious when you mentioned it, and yet I never saw that explanation before. Does the IEEE spec describe this simulation behaviour?
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Yes, but not that explicit. See Chapter "11. Scheduling Semantics" in IEEE Std 1364-2005. Here are some excerpts:pic.twitter.com/1cNtSm45FU
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