Hey twitterettes, I'm looking for a logic optimization tool that can create the most efficient expression that maps an n-bit input to a 1-bit output by specifying which input vectors that produce 1,0 or are allowed to be either. It takes time to do many of those by hand on paper
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Given the existing tooling, I agree. But there are things lost in the process that makes debugging harder. This can be improved by still sticking to verilog, but my feeling is that most new HDL devs are more interested in fixing their verilog pet peeves than taking care of this
A large percentage of those issues would be solved if those verilog code generators would simply output `line directives.
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Yes. And for some languages, human-readable names. Predictable names are also pretty important when you want to match constraints or attach debug probes after synthesis, so you don't have to redo that by hand every f-in time. :)
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Yes. Chisel is really bad wrt names. But a different IR wouldn't make a difference for this.
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