Hey twitterettes, I'm looking for a logic optimization tool that can create the most efficient expression that maps an n-bit input to a 1-bit output by specifying which input vectors that produce 1,0 or are allowed to be either. It takes time to do many of those by hand on paper
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But to achieve this we need better tooling and foundations. Standard libraries, a common IR that EDA tools can target directly. What
@M_Labs_Ltd and@whitequark do with nmigen is a step in the right direction in my opinion
Other people will vehemently disagree but imo, especially given the existing (open and closed source) software ecosystem, simple Verilog is a good intermediate representation for integrating designs created from different DSLs.
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Given the existing tooling, I agree. But there are things lost in the process that makes debugging harder. This can be improved by still sticking to verilog, but my feeling is that most new HDL devs are more interested in fixing their verilog pet peeves than taking care of this
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And again, this is something I wanted to write about for a long time, but the situation is very analogous to web browsers where everything had to pass through js at some point. Then asm.js came as an intermediate solution until vendors agreed on webassembly and everyone was happy
End of conversation
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