Hey twitterettes, I'm looking for a logic optimization tool that can create the most efficient expression that maps an n-bit input to a 1-bit output by specifying which input vectors that produce 1,0 or are allowed to be either. It takes time to do many of those by hand on paper
ABC does support don't cares, may be especially useful in cases where N is large.
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N is usually five in this case since the input is mostly rv32 opcodes, sometimes paired with a bit or two extra. Not sure five is considered large in this context :)
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And the target arch is 4 input LUTs?
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