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I have question. What does “without simulation” mean in the context of testing the core? The author mentions using riscv-formal before “simulation”. Presumably they mean “FPGA simulation”? i.e. RTL without tech mapping to FPGA i.e. synthesis? riscv-formal is in verilog?
Cool.
I must spend some time with riscv-formal. SpinalHDL is also interesting, another Scala DSL. BTW Bundles in Chisel are great. Apple’s Swift could also be used for a hw DSL due to operator overload (verbose without it). Reflection is also necessary for concise generators.
Verilog looks quite painful.
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