"A Bug-Free RISC-V Core without Simulation" by @tom_verbeure https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html …. Great article on riscv-formal. (And on how bad PicoRV32 is. Most of the criticism is justified. :)
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Then I will stay away from looking into the code and keep my vision of it as a pretty solid and flexible all-around CPU. I do happen to know there are far worse CPUs out there. Some that doesn't even pass formal verification. Can you believe that?
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I feel called out.
End of conversation
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