"A Bug-Free RISC-V Core without Simulation" by @tom_verbeure https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html …. Great article on riscv-formal. (And on how bad PicoRV32 is. Most of the criticism is justified. :)
PicoRV32 does not have two memory load units that are "combined internally". It's just one state machine that performs one memory op at a time.
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Ah ok. I haven't looked at the core in detail. Just assumed you had e.g. separate regs for PC and load/store address
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I think you are confusing PicoRV32 with any sane microarchitecture. :) PicoRV32 is an incoherent mess held together by duct tape and formal verification. I don't think it would even be humanly possible to build something like it without using formal tbh. :D
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