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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. whitequark‏ @whitequark 8 Dec 2018
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      so i just had an extremely, absurdly, unreasonably possible cursed idea, and @fpga_dave encouraged me with advice i'll just leave this herepic.twitter.com/iWkBpDd10T

      6 replies 2 retweets 36 likes
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    2. whitequark‏ @whitequark 8 Dec 2018
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      this is an FPGA made from 74xx-style discrete logic. the difference from http://blog.notdot.net/2012/10/Build-your-own-FPGA … is a) that this one is built from ground up (heavily drawing on iCE40) to support modern synthesis/P&R toolchains, and b) it's designed to use 3D routing, exploiting the medium!

      4 replies 2 retweets 19 likes
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    3. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Dec 2018
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      Replying to @whitequark

      The 3D routing will be a bit of a challenge in nextpnr. Especially for the GUI. Probably need to use some mapping to 2D to fit existing data structures, and use the inverse mapping inside of distance/delay estimation code.

      1 reply 0 retweets 1 like
    4. Dave  🏳️‍🌈‏ @fpga_dave 8 Dec 2018
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      Replying to @oe1cxw @whitequark

      I would think the bigger problem in terms of the nextpnr core would be the placer, which uses X/Y positions to determine position. The router just uses the delay estimates provided by the architecture, which could easily use a 3D model for these.

      1 reply 0 retweets 0 likes
    5. Dave  🏳️‍🌈‏ @fpga_dave 8 Dec 2018
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      Replying to @fpga_dave @oe1cxw @whitequark

      Maybe wirelength calculation should be done by the Arch API rather than the placer, for this reason...

      1 reply 0 retweets 0 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 8 Dec 2018
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      Replying to @fpga_dave @whitequark

      Otoh this is going to be a small device. Routing could surely be done without delay estimator and maybe a very simple custom placer would be the best choice for a _small_ 3D device.

      11:14 AM - 8 Dec 2018
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      • Dave 🏳️‍🌈 whitequark
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        1. Dave  🏳️‍🌈‏ @fpga_dave 8 Dec 2018
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          Replying to @oe1cxw @whitequark

          I guess minimising routing congestion is probably more of a concern than minimising critical path delay too, which strengthens the argument for a custom placer.

          0 replies 0 retweets 1 like
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