"A Bug-Free RISC-V Core without Simulation" by @tom_verbeure https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html …. Great article on riscv-formal. (And on how bad PicoRV32 is. Most of the criticism is justified. :)
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This, however, isn't true. PicoRV32 marks all instruction fetches exactly so that it is possible to split the memory interface into separate instruction and data busses for users that want that. </Nitpick>pic.twitter.com/t72b3IOKiV
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Replying to @oe1cxw
Perhaps he means that you cannot simultaneously fetch an instruction and perform a data load/store in the same cycle?
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Replying to @SamuelAFalvoII
PicoRV32 takes at least three cycles for each instruction. You couldn't do that anyways, even if it had two memory interfaces.
10:26 AM - 8 Dec 2018
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