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"A Bug-Free RISC-V Core without Simulation" by @tom_verbeure https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html …. Great article on riscv-formal. (And on how bad PicoRV32 is. Most of the criticism is justified. :)
This, however, isn't true. PicoRV32 marks all instruction fetches exactly so that it is possible to split the memory interface into separate instruction and data busses for users that want that. </Nitpick>pic.twitter.com/t72b3IOKiV
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