Here are my slides: http://www.clifford.at/papers/2018/riscv-formal/ …
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T - 90 minutes to my tutorial session at the RISC-V Summit. See you there! https://tmt.knect365.com/risc-v-summit/agenda/1#track-1_formal-verification-of-risc-v-processor-implementations-space-limited ….
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Would this recorded and posted later ?
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very interesting. How can I test circuit1 ? using gtkwave it is not possible to simulate well. Input and output of biestable are the same all time. I need put on a seconf biestable for simulate using gtkwave. Your recomend me other open source tool?pic.twitter.com/IP61tUo0H0
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