Comparing solvers. Here's the test: https://gitthub.com/ZipCPU/vgasim/blob/master/bench/formal/imgfifo.sby … The test includes a single proof of an async FIFO plus frame buffer reader/bus master. Boolector v3: 2hrs Yices: 38+ hours and still going abc pdr: 38+ hours and still going as well Feel free to try this out yourself
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Fixed link: https://github.com/ZipCPU/vgasim/blob/master/bench/formal/imgfifo.sby … (s/gitthub/github/)
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