Spent two days trying to figure out why the data bus address is stuck at 0 when running on FPGA by pulling out internal signals to pins and looking with a scope. (Thank god I got a 4ch scope at least). Right now it lools like a^b outputs a. Should probably take a step back
That would be great. Also: Just attempting to create an MCVE often leads us already directly to the answers we are looking for.
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Using my blinky design with one of the assumed broken pins work fine, so it might be an sw issue. Will try to recreate the broken design, but I changed things all over the place so I'm not sure I'm able to recreate it
Thanks. Twitter will use this to make your timeline better. UndoUndo
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