Spent two days trying to figure out why the data bus address is stuck at 0 when running on FPGA by pulling out internal signals to pins and looking with a scope. (Thank god I got a 4ch scope at least). Right now it lools like a^b outputs a. Should probably take a step back
-
-
No, I haven't. Assumed it is a hw error, but it's a bit unusual in my experience for these things to just break. Maybe I should test a simple test design just to make sure it's not some strange sw thing
-
That would be great. Also: Just attempting to create an MCVE often leads us already directly to the answers we are looking for.
- Show replies
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.