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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Olof Kindgren‏ @OlofKindgren 18 Nov 2018
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      • Report NetzDG Violation

      Doh! Just realized ice40 FFs don't support initial values. Running the synthesized netlist in icarus just gives me a ton of angry red lines. No wonder it didn't work on real hw :/

      2 replies 1 retweet 10 likes
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    2. whitequark‏ @whitequark 18 Nov 2018
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      Replying to @OlofKindgren

      the FOSS toolchain uses the invert muxes before and after the FF to fake those

      1 reply 0 retweets 5 likes
    3. Olof Kindgren‏ @OlofKindgren 18 Nov 2018
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      Replying to @whitequark

      I read that in an old bug report, but something still seems fishy. It could also just be that the simulation primitives doesn't implement preset values. Adding explicit reset to a couple of control plane signals allowed me to do netlist simulation. Haven't tested on hw yet

      1 reply 0 retweets 0 likes
    4. Dave  🏳️‍🌈‏ @fpga_dave 18 Nov 2018
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      Replying to @OlofKindgren @whitequark

      They do definitely initialize to 0 in hardware

      1 reply 0 retweets 1 like
    5. Olof Kindgren‏ @OlofKindgren 18 Nov 2018
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      Replying to @fpga_dave @whitequark

      I would assume so, and with the inverting that @whitequark mentioned, I should be safe. Conclusion is that the simulation primitives are wrong here. The problem is also somewhere else, since I just verified it still doesn't work on hw

      1 reply 0 retweets 1 like
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 18 Nov 2018
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      Replying to @OlofKindgren @fpga_dave @whitequark

      If it doesn't work in sim, and doesn't work in hardware, then there's nothing thete to support the conclusion that the sim primitives are broken afaict. 🤓 If there's a problem we'll be happy to look at an MCVE that demonstrates it and we'll try to fix the issue.

      11:18 PM - 18 Nov 2018
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        1. New conversation
        2. Olof Kindgren‏ @OlofKindgren 19 Nov 2018
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          Replying to @oe1cxw @fpga_dave @whitequark

          Yeah, I can see that my case isn't very strong with the info I provided, but I made an MCVE nowhttps://github.com/YosysHQ/yosys/issues/703 …

          1 reply 0 retweets 0 likes
        3. Olof Kindgren‏ @OlofKindgren 19 Nov 2018
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          Replying to @OlofKindgren @oe1cxw and

          At least I think I did. Realized I'm not really sure what an MCVE means :)

          0 replies 2 retweets 0 likes
        4. End of conversation

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