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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      After a few hours playing around with #CLaSH, I've implemented ADDI, SLTI(U), XORI, ORI, ANDI, SLLI, SRLI, and SRAI for my @risc_v processor. @OlofKindgren is way ahead of me though :D #FPGA

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    2. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      All ALU instructions are done!

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    3. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      Just as I'm done with the ALU instructions, I receive @krtkl_inc's SnickerDoodle from @crowd_supply! Coincidence? I think not :D

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    4. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      pic.twitter.com/cvblssCcFL

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    5. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      Conditional and unconditional branches are also done.

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    6. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      CLISC-V, a RISC-V (RV32I) processor written in #CLaSH, a functional hardware description language.https://gitlab.com/GuzTech/clisc-v 

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    7. 天 Oğuz Meteer 天‏ @BitlogIT 3 Nov 2018
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      For those who prefer GitHub:https://github.com/GuzTech/clisc-v 

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      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 4 Nov 2018
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      Replying to @BitlogIT

      👍 Just let me know if you need any help with riscv-formal.pic.twitter.com/CpBu98Z408

      1:23 AM - 4 Nov 2018
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      • 天 Oğuz Meteer 天 Ghosteen
      0 replies 1 retweet 1 like

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