Does syntheis tools (especially yosys) choose the most efficient encoding for muxes if I set the default choice to x? e.g. wire [1:0] q = (cond_a) ? 2'b00 : (cond_b) ? 2'b01 : 2'bxx; VHDL has an explicit don't care ('-'). Haven't thought of how verilog handles that
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Cool. That sounds to me like the sane way to do it :) But it also seems to be a safer choice to rewrite to casez as
@maxslug also proposed
