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oe1cxw's profile
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen 🏳️‍⚧️🏳️‍🌈🧙🏻‍♀️ BLM 🏴🚩
Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩
@oe1cxw

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Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

@oe1cxw

Neurodiverse trans geek girl. Yosys, RISC-V, SAT/SMT.

She/her/hers
clairexen.net
Joined September 2014

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    1. Geoff Langdale‏ @geofflangdale 31 Oct 2018
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      @johnregehr Are there good papers with details on the SMT formulation of CEGIS for superoptimization aside from Gulwani et al and the Souper paper itself (and source)? The whole thing seems alarmingly.. magical. I feel like an ape poking the monolith with a stick when I use Z3.

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    4. Geoff Langdale‏ @geofflangdale 31 Oct 2018
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      Replying to @johnregehr

      I like this. I'm working on enumerating fairly abstract DAGs (where all unary, binary and ternary ops are treated as the same) and sorting by cost (esp. longest path length or a rough latency estimate). Am thinking about approx. cost for throughput as well, which would mean ...

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    5. Geoff Langdale‏ @geofflangdale 31 Oct 2018
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      Replying to @geofflangdale @johnregehr

      ... enumerating based on port assignment as well. The plan is to do constant synthesis and op selection in Z3 one after the other. I'm not sure how much stupid work is getting redone in this world, though - Z3 might do 3/4 of my ops and find that nothing is going to work....

      2 replies 0 retweets 1 like
    6. Michael  🍊‏ @contramork 31 Oct 2018
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      Replying to @geofflangdale @johnregehr

      I’m curious how @oe1cxw created RISC-V instruction decoders using z3 descriptions of bit manipulation intrinsics. Seems to require “column generation” as the number of instructions is not known a priori. V.clever. This example uses conditional holes: https://www.cs.cornell.edu/~asampson/blog/minisynth.html …

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    7. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Nov 2018
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      Replying to @contramork @geofflangdale @johnregehr

      I'm usually not using z3 but yices2 and boolector. They are many many times faster for the kind of problems I'm looking at. I've never built a risc-v insn decoder for program synthesis. Usually that's one abstraction level up, see for example http://svn.clifford.at/handicraft/2018/xbitpermsyn/ ….

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    8. Michael  🍊‏ @contramork 1 Nov 2018
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      Replying to @oe1cxw @geofflangdale @johnregehr

      Ok interesting. Thanks for sharing your program. I was puzzling over how one would express this in z3 (synthesizing RISC-V immediate decode programs) and thought the problem space was large. I see you add 3 instructions (syn.addcommand(...)) in make_riscv_b.py.

      1 reply 0 retweets 1 like
    9. Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Nov 2018
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      Replying to @contramork @geofflangdale @johnregehr

      Yes. This only looks at programs with three sequential instructions, each one of them can be rori, grevi, or gzip (gzip is the old name for shfli/unshfli). This program produces a permutation that has the imm bits in the right order but interleaved with other bits. -> bext

      1 reply 0 retweets 3 likes
      Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩‏ @oe1cxw 1 Nov 2018
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      Replying to @oe1cxw @geofflangdale @johnregehr

      I'd love to be able to also generate things like that bext and the final shifts with a solver, but solving for the 2nd parameter of bext is a pretty hard smt problem, in part because I am not aware of any efficient smt encoding for the bext operation.

      1:19 AM - 1 Nov 2018
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      • John Regehr Michael 🍊 Geoff Langdale
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