My @risc_v core can now do jal, addi, lui and lb. At least until I improve my testing and see that they are all broken
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Have you considered implementing RVFI (risc-v formal interface) so you can check your new core formally? I'd help setting up riscv-formal if you implement the interface.https://github.com/cliffordwolf/riscv-formal/blob/master/docs/rvfi.md …
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Awesome. I've been meaning to do that. Already have the RVFI interface implemented, but wanted some help with the glue logic. Hopefully this will eventually result in a SymbiYosys backend for Edalize too
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Cool! -> DM
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