Claire Xen  🏳️‍⚧️ 🏳️‍🌈 🧙🏻‍♀️ BLM  🏴 🚩

This is the most pointless exercise I have seen in a long time, and I absolutely love it. :) Maybe we can use it to hide messages in binaries by encoding it as different kind of NOPshttps://twitter.com/wavedrom/status/1055277879309697024 …

hm, I wonder if we can find a *useful* sub-ISA based on RVC that works on the "don'tcares" in these NOP implementations; e.g. if you advance PC by 2 (instead of 4) once, end up in 4B-strided compressed instruction sequences *embedded* in NOPs that still works as a sensible ISA.

Now we are in a *useful* mood again -- it should be a good test for the processor implementation passing long random NOP sequence and expect no architectural state change. Or even some way feeding it into a formal flow? @oe1cxw ?

far as I can tell, for the ISA, if you go the formal route, proof that none of the instructions in isolation change state is enough to prove no sequence does. Of course, with pipelining and OoO exec, you'd need to look at complete pipeline states instead of indiv. instructions.

I was thinking the same thing. Just looked into riscv-formal yesterday and that should do the job, granted that the formal properties have it covered