If you create a delayed clock to work around a broken simulation (assign clk_1 = #1 clk;), even if clk_1 is fed to only one module, Vivado renames the entire clk net to clk_1, so all TCL commands using clk now must use clk_1! Need a better solution for bad sims. #FPGA
Simply setting (* KEEP="TRUE" *) or (* DONT_TOUCH="TRUE" *) on clk should make sure this is the signal name that survives synthesis.
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Aha. Of course! I already use DONT_TOUCH to prevent optimizing away incomplete module logic when initially estimating area and floorplanning, and now you've given me a new regular use for it. Thanks! :)
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