Does anyone know of any free tool to visualize a tree of verilog modules to an SVG or similar? Like most commercial EDA tools have a schematic view of the digested HDL. AFAIU, yosys can output SVG but will break the design down to individual primitives
-
Parse Yosys "hierarchy" or "stat" output and generate a dot file from that data? Or simply write a small yosys pass..
I can add an option to "stat" for writing a dot file if you provide a template/example dot file that produces a fancy nice looking graph that I can use as reference so I don't need to spend an afternoon digging through the graphviz documentation.
-
-
Cool! That would be useful. I'm considering a FuseSoC backend that just creates various design metrics and info. Will let you know when I have a pretty template. I will likely outsource this to someone else though, for the same reasons you cited :)
Thanks. Twitter will use this to make your timeline better. UndoUndo
-
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.