Xilinx Vivado seems to think that this is synthesizable since Vivado 2017.3. Opinions anyone? (SV code, TCL, and Vivado logs at http://svn.clifford.at/handicraft/2018/vivadohier ….)pic.twitter.com/MgpgP76B7g
Show this thread
-
If the target code will *never* need to be read by a human then you may have an argument in favor. In that case though, why even bother with hierarchy? Just load it all into on flat module.
This is about a specific code generator and that's just not what it does. It creates many modules that form a hierarchy and then uses hierarchical references between them. It's not my generator. I can't just make it output a flat module.